/*
 * (C) Copyright 2006-2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <nand.h>
#include <asm/io.h>
#include "preloader.h"

#define CONFIG_SYS_NAND_READ_DELAY \
	{ volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }

//static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;

#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
/*
 * NAND command for small page NAND devices (512)
 */
static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
{
	struct nand_chip *this = mtd->priv;
	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;

	if (this->dev_ready)
		while (!this->dev_ready(mtd))
			;
	else
		CONFIG_SYS_NAND_READ_DELAY;

	/* Begin command latch cycle */
	this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
	/* Set ALE and clear CLE to start address cycle */
	/* Column address */
	this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
	this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
	this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
		       NAND_CTRL_ALE); /* A[24:17] */
#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
	/* One more address cycle for devices > 32MiB */
	this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
		       NAND_CTRL_ALE); /* A[28:25] */
#endif
	/* Latch in address */
	this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

	/*
	 * Wait a while for the data to be ready
	 */
	if (this->dev_ready)
		while (!this->dev_ready(mtd))
			;
	else
		CONFIG_SYS_NAND_READ_DELAY;

	return 0;
}
#else
/*
 * NAND command for large page NAND devices (2k)
 */
static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
{
	struct nand_chip *this = mtd->priv;
	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;

	if (this->dev_ready)
		while (!this->dev_ready(mtd))
			;
	else
		CONFIG_SYS_NAND_READ_DELAY;

	/* Emulate NAND_CMD_READOOB */
	if (cmd == NAND_CMD_READOOB) {
		offs += CONFIG_SYS_NAND_PAGE_SIZE;
		cmd = NAND_CMD_READ0;
	}

	/* Begin command latch cycle */
	this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
	/* Set ALE and clear CLE to start address cycle */
	/* Column address */
	this->cmd_ctrl(mtd, offs & 0xff,
		       NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
	this->cmd_ctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
	/* Row address */
	this->cmd_ctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
	this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff),
		       NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
	/* One more address cycle for devices > 128MiB */
	this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
		       NAND_CTRL_ALE); /* A[31:28] */
#endif
	/* Latch in address */
	this->cmd_ctrl(mtd, NAND_CMD_READSTART,
		       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
	this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

	/*
	 * Wait a while for the data to be ready
	 */
	if (this->dev_ready)
		while (!this->dev_ready(mtd))
			;
	else
		CONFIG_SYS_NAND_READ_DELAY;

	return 0;
}
#endif

static int nand_is_bad_block(struct mtd_info *mtd, int block)
{
	struct nand_chip *this = mtd->priv;

	nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);

	/*
	 * Read one byte
	 */
	if (readb(this->IO_ADDR_R) != 0xff)
		return 1;

	return 0;
}


/* Modified by warits to fit iMAPx200 NAND controller */
static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
{
	struct nand_chip *this = mtd->priv;
	u_char *ecc_calc;
	u_char *ecc_code;
	u_char *oob_data;
	int i;
	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
	int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
	int eccoffs = CONFIG_SYS_NAND_OOBSIZE - eccbytes * eccsteps;
	uint8_t *p = dst;
	int col;
#if defined(CONFIG_SYS_NAND_MLC)
	u_long nfmeccd0, nfmeccd1, nfmeccd2;
#endif

	nand_command(mtd, block, page, CONFIG_SYS_NAND_PAGE_SIZE, NAND_CMD_READ0);

	/* No malloc available for now, just use some temporary locations
	 * in SDRAM
	 */
	ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
	oob_data = ecc_calc + 0x200;

	/* Read the ECC codes into ecc_code */
	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);

	/* If this is a free page, return 0xff values without reading */
	if(*(uint8_t *)(oob_data + CONFIG_SYS_NAND_DIRTYMARK + 3) == 0xff)
	{
		for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE >> 2); i++)
		  *(u_long *)(p + i * 4) = 0xffffffff;
		return 0;
	} else
	  ecc_code = oob_data + eccoffs;

	col = 0;
	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
		/* Begin command latch cycle */
		this->cmd_ctrl(mtd, NAND_CMD_RNDOUT, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
		/* Set ALE and clear CLE to start address cycle */
		/* Column address */
		this->cmd_ctrl(mtd, col & 0xff,
		   NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
		this->cmd_ctrl(mtd, (col >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
		this->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);

		/* Write relative ECC into NFMECCDX */
#if defined(CONFIG_SYS_NAND_MLC)
		nfmeccd0 =	*(ecc_code + i) |
			*(ecc_code + i + 1) << 8 |
			*(ecc_code + i + 2) << 16 |
			*(ecc_code + i + 3) << 24;

		nfmeccd1 =	*(ecc_code + i + 4) |
			*(ecc_code + i + 5) << 8 |
			*(ecc_code + i + 6) << 16 |
			*(ecc_code + i + 7) << 24;

		nfmeccd2 =	*(ecc_code + i + 8);

		writel(nfmeccd0, NFMECCD0);
		writel(nfmeccd1, NFMECCD1);
		writel(nfmeccd2, NFMECCD2);
#else
		writel(cpu_to_le32(*(u_long *)(ecc_code)), NFMECCD0);
#if defined(CONFIG_SYS_NAND_BUSW16)
		writel(cpu_to_le32(*(u_long *)(ecc_code + 4)), NFMECCD1);
#endif
#endif

		this->ecc.hwctl(mtd, NAND_ECC_READ);
		this->read_buf(mtd, p, eccsize);
		/* No chance to do something with the possible error message
		 * from correct_data(). We just hope that all possible errors
		 * are corrected by this routine.
		 */
		this->ecc.correct(mtd, p, NULL, ecc_code + i);

		col = eccsize * (CONFIG_SYS_NAND_ECCSTEPS + 1 - eccsteps);
	}
	return 0;
}

static int nand_load(struct mtd_info *mtd, unsigned int offs,
		     unsigned int uboot_size, uchar *dst)
{
	unsigned int block, lastblock;
	unsigned int page;

	/*
	 * offs has to be aligned to a page address!
	 */
	block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
	lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
	page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;

	while (block <= lastblock) {
		if (!nand_is_bad_block(mtd, block)) {
			/*
			 * Skip bad blocks
			 */
			while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
				nand_read_page(mtd, block, page, dst);
				dst += CONFIG_SYS_NAND_PAGE_SIZE;
				page++;
			}

			page = 0;
		} else {
			lastblock++;
		}

		block++;
	}
	boot_set_stat2((uint16_t)lastblock);

	return 0;
}

/*
 * The main entry for NAND booting. It's necessary that SDRAM is already
 * configured and available since this code loads the main U-Boot image
 * from NAND into SDRAM and starts it from there.
 */
void nand_boot(void)
{
	struct nand_chip nand_chip;
	nand_info_t nand_info;
	int ret;
	__attribute__((noreturn)) void (*uboot)(void);


	/* Reconfig and init DDR2 */
#ifdef CONFIG_SYS_MEMTYPE_DDR2_PRO
	//denali_test();
#endif

	/*
	 * Init board specific nand support
	 */
	nand_info.priv = &nand_chip;
	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void  __iomem *)CONFIG_SYS_NAND_BASE;
	nand_chip.dev_ready = NULL;	/* preset to NULL */

	/* Call board specific init function */
	board_nand_init(&nand_chip);

	if (nand_chip.select_chip)
		nand_chip.select_chip(&nand_info, 0);

#if 0
	/*
	 * Load u1 image from NAND into RAM
	 */
	ret = nand_load(&nand_info, CONFIG_SYS_NAND_U1_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
			(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);

	/* Check u1 validity */
	uboot = check_ubimg();
	if(likely(uboot))
	{
		boot_set_stat(CONFIG_BOOTSTAT_U1);
		goto __ram_boot__;
	}

	/*
	 * Load u2 image from NAND into RAM
	 */
	ret = nand_load(&nand_info, CONFIG_SYS_NAND_U2_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
			(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);

	/* Check u2 validity */
	uboot = check_ubimg();
	if(likely(uboot))
	{
		boot_set_stat(CONFIG_BOOTSTAT_U2);
		goto __ram_boot__;
	}
#endif
	/*
	 * Load u0 image from NAND into RAM
	 */
	ret = nand_load(&nand_info, CONFIG_SYS_DISK_U0_OFFS, CONFIG_SYS_DISK_U_BOOT_SIZE,
			(uchar *)(CONFIG_SYS_NAND_U_BOOT_DST + 0x40));

	/* We don't check u0 validity and derictly jump to this uboot image */
	boot_set_stat(CONFIG_BOOTSTAT_U0);
	uboot = (void *)(CONFIG_SYS_DISK_U_BOOT_DST + 0x40);


	if (nand_chip.select_chip)
		nand_chip.select_chip(&nand_info, -1);

	/*
	 * Jump to U-Boot image
	 */
	(*uboot)();
}

#if 0
/*
 * Called in case of an exception.
 */
void hang(void)
{
	/* Loop forever */
	while(1) ;
}
#endif
